(1) Field of the Invention
The present invention relates to a method of fabricating a metal-insulator-metal capacitor, and more particularly, to a method of forming an improved metal-insulator-metal capacitor in the fabrication of an integrated circuit device.
(2) Description of the Prior Art
Capacitors are critical components in the integrated circuit devices of today. Both polysilicon-insulator-polysilicon and metal-insulator-metal (MIM) capacitors have been used in the art. Polysilicon to polysilicon or polycide to polycide (PIP) capacitors perform at a high parasitic capacitance. Parasitic capacitance is calculated as the ratio of the Ccapacitor to Csubstrate, where Ccapacitor is the capacitance between the capacitor plates and Csubstrate is the capacitance between the top plate or bottom plate of the capacitor to the silicon substrate. Generally, the parasitic capacitance for PIP capacitors is about 10%, but for MIM capacitors, the parasitic capacitance can be lower than 5%.
The process flow for making a polysilicon to polysilicon or polycide to polycide capacitor is not transparent to present or future CMOS technology. That is, the introduced thermal budget for making the PIP capacitor will affect the MOS devices with extra dopant diffusion effect. It is desirable that the capacitor process module be transparent to the present and future CMOS technology. Also, a high quality insulator must be provided within the capacitor.
U.S. Pat. Nos. 5,576,240 and 5,654,581 to Radosevich et al, 5,479,316 to Smrtic et al, 5,708,559 to Brabazon, 5,406,447 to Miyazaki, 5,741,721 to Stevens, and 4,971,924 to Tigelaar et al all disclose various methods of forming metal-insulator-metal capacitors. U.S. Pat. No. 5,589,416 to Chittipeddi teaches fabrication of a metal-oxide-polysilicon capacitor. U.S. Pat. Nos. 5,554,558 to Hsu et al, 5,338,701 to Hsu et al and 5,037,772 to McDonald teach methods of fabricating polysilicon to polysilicon or polycide to polysilicon capacitors. U.S. Pat. No. 4,697,330 to Paterson et al discloses a very high integrity capacitor dielectric in a polysilicon to polysilicon or polysilicon to metal capacitor.